FIELD OF THE INVENTION
The invention relates to a semiconductor memory having inverted and non-inverted bit lines as well as corresponding collective lines and switching transistors connecting them.
As described in U.S. Pat. No. 4,875,192, a semiconductor memory contains a regular, matrix-like configuration of memory cells for storing binary data. A memory cell essentially contains an access transistor and a storage capacitor for storing an information bit. A multiplicity of memory cells are connected to a bit line. The information to be written to and read from the memory cell is provided via the bit line. The desired memory cell is selected via a word line. During the read-out operation, a sense amplifier amplifies the signal read from the memory cell. After the amplification operation, the bit line is connected to a collective line via a switching transistor, the collective line leading to the output of the semiconductor memory.
The sense amplifier is configured as a differential amplifier.
A respective bit line is connected to the differential inputs of the differential amplifier. In a memory cell, either the information bit to be stored is itself stored or its inverted data value is stored, this depending on the differential amplifier input to which the bit line assigned to the memory cell is connected. A bit line has connected to it either only memory cells in which the data information is stored in a non-inverted fashion, or only memory cells in which the data information is stored in an inverted fashion. The corresponding bit lines are therefore referred to as non-inverted or inverted bit lines. Inverted and non-inverted bit lines are disposed alternately next to one another in the configuration shown in U.S. Pat. No. 4,875,192.
U.S. Pat. No. 5,280,443 describes a semiconductor memory in which the bit lines are transposed in order to avoid unbalanced capacitive loading on the bit lines during a memory access. At the sense amplifier end of the bit lines, in each case two inverted and two non-inverted bit lines lie next to one another. The bit lines can be switched to an inverted or non-inverted collective line via switching transistors. In this case, inverted and non-inverted bit lines can be connected to the same collective line.